The present invention relates to semiconductor devices, and particularly to recessing the gate dielectric and work function metals of a replacement metal gate field effect transistor (FET).
FETs are commonly employed in electronic circuit applications. FETs may include a source region and a drain region spaced apart by a semiconductor channel region. In planar FETs, the semiconductor channel region may be a semiconductor substrate. In finFETs, the semiconductor channel region may be a semiconductor fin. A gate, potentially including a gate dielectric layer, a work function metal layer, and a metal electrode, may be formed next to the channel region. By applying voltage to the gate, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.
Due in part to the relative instability of the dielectric layer and work function metal layer of the gate, a gate-last process, or replacement metal gate process, may be used where a sacrificial gate is formed prior to forming other components of the FET. The sacrificial gate may then be removed to form a recessed region that may then be filled with a replacement metal gate potentially including a gate dielectric layer, a work function metal layer, and a metal electrode. Because the replacement metal gate is formed after the other components of the FET, it is not subjected to various potentially damaging processing steps, for example high-temperature anneals. Prior to forming the metal electrode, the gate dielectric layer and the work function metal layer may be recessed to a height less than the height of the recessed region to reduce the gate resistance.